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Idiomas disponibles
Idiomas disponibles
3. CARTRIDGE CONNECTORS
Pin
49
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Pin
50
2
Pin
Name
I/O
Pin
Name
I/O
1
CS1
0
2
CS2
0
3
CS12
0
4
SLTSL
0
5
Reserve
6
RFSH
0
7
WAIT
I
8
INT
I
9
M1
0
10
BUSDIR
I
11
IORQ
0
12
MERO
0
13
WR
0
14
RD
0
15
RESET
0
16
Reserve
17
A9
0
18
A15
0
19
A11
0
20
A10
0
21
A7
0
22
AS
0
23
A12
0
24
AS
0
25
A14
0
26
A13
0
27
A1
0
28
AO
0
29
A3
0
30
A2
0
31
AS
0
32
A4
0
33
D1
I/O
34
DO
I/O
35
D3
I/O
36
D2
I/O
37
D5
I/O
38
D4
I/O
39
D7
I/O
40
D6
I/O
41
GND
42
CLOCK
0
43
GND
44
SW1
45
-sv
46
SW2
47
-sv
48
+
12V
49
SOUN DIN
50
-12V
Pin
Name
Content
1
CS1
ROM addresses 4000 - 7FFF select signal
2
CS2
ROM addresses 8000 - BFFF select signal
3
CS12
ROM addresses 4000 -cBFFF select signal (for 256k ROM)
4
SLTSL
Slot select signal
5
Reserve
Reserved signal line - use inhibited
6
RFSH
Refresh cycle signal
7
WAIT
CPU's WAIT request signal
8
INT
Interrupt request signal to CPU
9
M1
Signal expressing CPU fetch cycle
10
BUSDIR
This signal con'trols direction of external data bus buffer
Cartridges are selected and L level is output from each
cartridge at data transmission time
11
IORQ
I/O request signal
12
MERO
Memory request signal
13
WR
Write timing signal
14
RD
Read timing signal
15
RESET
System reset signal
16
Reserve
Reserved signal line - use inhibited
17-32
AO-A15
Address bus signals
50
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