TRIGGER/GATE IN
Frequency Range:
Signal Range:
Trigger Delay:
Gate Delay:
Minimum Pulse Width:
Input Impedance:
MAIN 50Ω OUTPUT
Amplitude:
V
low:
OUT
Rise/Fall Times:
Aberrations:
AUX OUTPUT
SYNC OUTPUT
Amplitude:
Timing:
Duration:
GENERAL
Power:
Operating Range:
Storage Range:
Environmental:
Safety:
EMC:
Size:
Weight:
4
DC - 10MHz
Threshold nominally TTL level;
Typically 100ns from trigger edge to MAIN OUT transition.
Approximately 20% of the PERIOD range setting +80ns from gate leading
edge to MAIN OUT transition.
>30ns.
Typically 10kΩ.
Two switch selectable ranges of 0·1V - 1·0V and 1V - 10V from 50Ω.
(50mV to 500mV and 500mV to 5V into 50Ω). Adjustable within ranges by
a single turn vernier.
<5% of Amplitude +100mV (1V-10V range).
Typically 10ns into 50Ω load.
Maximum 15ns.
Typically <5%, for output set at >20% of range maximum, into 50Ω.
CMOS/TTL level, signal with the same timings as MAIN OUT; leads MAIN
OUT by typically 15ns.
A positive going pulse at CMOS/TTL level.
Leading edge occurs typically 40ns before the MAIN OUT transition in all
pulse modes and typically 10ns after MAIN OUT in Square mode.
Typically 30ns.
220V-240V or 110V-120V AC ±10%, 50/60Hz, adjustable internally;
20VA max. Installation Category II.
+ 5°C to 40°C, 20-80% RH.
-40°C to 70°C.
Indoor use at altitudes up to 2000m, Pollution Degree 2.
Complies with EN61010-1.
Complies with EN61326.
220(W) x 130(H) x 230(D)mm, excluding feet.
1·6kg.
maximum input ±10V.