Fujitsu SPARC M12-2S Guia De Instalacion página 278

/pci@8100/pci@4/pci@0/pci@1
/pci@8100/pci@4/pci@0/pci@0
/pci@8100/pci@4/pci@0/pci@1/usb@0
/pci@8100/pci@4/pci@0/pci@1/usb@0/hub@5
/pci@8100/pci@4/pci@0/pci@1/usb@0/hub@1
/pci@8100/pci@4/pci@0/pci@0/scsi@0
/pci@8100/pci@4/pci@0/pci@0/scsi@0/disk
/pci@8100/pci@4/pci@0/pci@0/scsi@0/tape
/pci@8000/pci@4
/pci@8000/pci@4/pci@0
/pci@8000/pci@4/pci@0/pci@11
/pci@8000/pci@4/pci@0/pci@0
/pci@8000/pci@4/pci@0/pci@0/network@0,1
/pci@8000/pci@4/pci@0/pci@0/network@0
Omitido
PSB Test Fault
---- ------- --------
00-0 Passed Normal
XSCF>
Ejemplo: ejemplo de ejecución para el SPARC M12-2S en una configuración de 3BB
(finalizado normalmente), incluida la ejecución de show-devs y probe-scsi-all
XSCF> testsb -v -p -s -a -y
Initial diagnosis is about to start, Continue?[y|n] : y
PSB power on sequence started.
LSB#01: POST 5.6.0 (2016/08/25 09:01)
POST Sequence 01 Banner
LSB#00: POST 5.6.0 (2016/08/25 09:01)
LSB#02: POST 5.6.0 (2016/08/25 09:01)
POST Sequence 02 CPU Check
POST Sequence 03 CPU Register
POST Sequence 04 STICK Increment
POST Sequence 05 Extended Instruction
POST Sequence 06 MMU
POST Sequence 07 Memory Initialize
POST Sequence 08 MSCAN
POST Sequence 09 Cache
POST Sequence 0A Interrupt Queue
POST Sequence 0B Floating Point Unit
POST Sequence 0C Encryption
POST Sequence 0D Random number
POST Sequence 0E Cacheable Instruction
POST Sequence 0F Softint
POST Sequence 10 CPU Cross Call
POST Sequence 11 CMU-CH
POST Sequence 12 PCI-CH
POST Sequence 13 TOD
POST Sequence 14 MBC Check Before STICK Diag
POST Sequence 15 STICK Stop
POST Sequence 16 STICK Start
POST Sequence 17 CPU Speed Control
POST Sequence 18 SX
POST Sequence 19 RT
Guía de instalación de Fujitsu SPARC M12-2S ･ Julio de 2018
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