Diagrama De Bloques De Camino De Entrada / Grabación De Video - LG DR-7621M Manual De Servicio

4. DIAGRAMA DE BLOQUES DE CAMINO DE ENTRADA / GRABACIÓN DE VIDEO
ANALOG VIDEO EE / REC
ITU-R.BT656 format : 8Bit Data & Data Clock
3-state-buffer is disabled and buffer output is High-Z state.
VIN_CLK (Data Clock:27MHz) is generated from TVP5146.
V1_ IN
V2_ IN
Y_ IN
C_ IN
27MHz
74HCU04
74HCU04
IC503
IC503
CS982_CLK
I2C Contro l
MPEG
DECODER
CS98300
IC301
1
80
TU_V_IN
75Ω
7
100KΩ
VIDEO
75Ω
DECODER
8
TVP5146
IC501
75Ω
17
I2C Contro l
75Ω
43,44,45,46
40
47,50,51,52
High
Impedance
state 7,75
SYSCLK
MPEG
73
9 8 Encoder
10 CS92686
IC503
74LCX125
63,64,65,66
67,70,71,72
'H'
DV_PASSn
183
YIN[7:0]
VIN_CLK
I2C Control
131
R.656 Data From A.Video IN
57,58,59,60 27MHz: A.Video In
102,103,104,106
ITU-R.BT656 format : 8Bit Data & Data Clock
TVP5146 Clock Output is High-Z State by IIC control.
3-state-buffer is Enabled by enable pin ìLowî state
VIN_CLK (Data Clock:27MHz) is generated from IC503.
RF SIGNAL
TUNER
TUNER
I2C Contro l
High
Impedance
state
27MHz
74HCU04
74HCU04
9
IC503
IC503
IC503
CS982_CLK
74LCX125
I2C Contro l
IC201
DV_PASSn
183
MPEG
DECODER
131
CS98300
IC301
57,58,59,60
102,103,104,106
3-17 3-18
DV1394 EE / REC
24.576MHz
VIDEO
1394 PHY
1394 PHY
DECODER
TSB41AB1
TSB41AB1
TVP5146
IC401
IC401
IC501
40
PD[7:0]
7,75
SYSCLK
MPEG
73
8
Encoder
10
CS92686
IC201
63,64,65,66
'L' 67,70,71,72
VIN_CLK
I2C Contro l
YIN[7:0]
R.656 Data From DV1394 IN
27MHz: DV1394 IN
TPA+/-
TPB+/-