OEL Active
(Input Buffer)
UEL Active
(Input Buffer)
SCL Active
(Input Buffer)
Layer 1
Gate 01
V/Hz Limiter Active
(Input Buffer)
Setpoint Adjustment
High Limit
(Input Buffer)
Setpoint Adjustment
Low Limit
(Input Buffer)
Unit Mode
(Input Buffer)
Soft Start
(Input Buffer)
Loss of
Isolation Module
Active
(Input Buffer)
Failed to Build Up
Active
(Input Buffer)
EDM Open Active
(Input Buffer)
EDM Shorted Active
(Input Buffer)
Generator Overvoltage
Active
(Input Buffer)
Generator Undervoltage
Active
(Input Buffer)
Loss of Field
Active
(Input Buffer)
V/Hz Protection
Active
(Input Buffer)
Field Overtemperature
Active
(Input Buffer)
Field Overvoltage
Active
(Input Buffer)
Loss of Sensing
Active
(Input Buffer)
Field Overcurrent
MUX
Active
(Input Buffer)
x
1
Layer 1
Gate 04
OEL Active
(Input Buffer)
UEL Active
(Input Buffer)
9369772990 Rev V
Underfrequency
Active
(Input Buffer)
Layer 1
Layer 1
Gate 02
Timer 1
Mode = Pickup/Dropout
T1 Time Delay = 10,000
T2 Time Delay = 0
Layer 2
Timer 1
Mode = Pickup/Dropout
T1 Time Delay = 0
T2 Time Delay = 10,000
MUX
u
1
x
u
1
2
u
3
u
u
u
4
4
4
Layer 1
Gate 03
Layer 1
Gate 04
Layer 1
Gate 05
u
1
u
2
u
3
u
u
u
4
4
4
Figura A-14. DECS-400 doble sin PSS (Parte 3 de 3)
Lógica programable del DECS-400
MUX
u
1
u
x
1
2
u
3
u
u
u
4
4
4
Layer 1
Gate 03
Layer 2
Gate 03
Layer 4
Gate 04
Layer 3
Gate 03
Layer 1
Gate 04
Layer 1
Gate 06
OEL activo
(Búfer de entrada)
UEL activo
(Búfer de entrada)
Output Relay #3
Common Limiter(s)
(Output Buffer)
Transfer to FCR on
Loss of Sensing
Enable
(Output Buffer)
Layer 2
Gate 01
Relay Output #2
Common Alarm
(Output Buffer)
Layer 2
Gate 02
P0072-93
Relay Output #4
Field Overcurrent
(Output Buffer)
A-29