Ssi Interface; Principle - Balluff BTL7-S5 Serie Manual De Instrucciones

BTL7-S5_ _(B) -M _ _ _ _ -P-S32/S115/S147/KA_ _/FA_ _
Magnetostrictive Linear Position Sensor – Profile Style
6

SSI interface

6.1

Principle

SSI stands for Synchronous Serial Interface and describes
a digital synchronous interface with a differential clock line
and a differential data line.
With the first falling cycle edge, the data word to be output
is buffered in the BTL to ensure data consistency. Data
output takes place with the first rising cycle flank, i.e. the
BTL supplies a bit to the data line for each rising cycle
edge. In doing so, the line capacities and delays of drivers
t when querying the data bits must be taken into account
v
in the controller.
The max. clock frequency f
length (see Technical data on page 20, Fig. 8-2). The t
time, also called monoflop time, is started with the last
falling edge and is output as the low level with the last
rising edge. The data line remains at low until the t
has elapsed. Afterwards, the BTL is ready again to receive
the next clock package.
SSIn
T
Clk
Clk
1
Data
MSB
T
Clk
Clk
t
Data
Clk
Data
T = 1 / f SSI clock period = 1/SSI clock frequency
Clk Clk
T = 1/f Sampling period = 1/sampling rate
A A
n Number of bits to be transmitted (requires n+1 clock impulses)
t = 2 · T Time until the SSI interface is ready again
m Clk
t = 150 ns Transmission delay times (measured with a 1 m cable)
v
14 english
is dependent on the cable
Clk
m
time
m
2 3 4 5
t
v v
T
A
With the BTL7-S_ _B-M..., position data is determined
and output in a timely manner and synchronous to the
external sampling period. For synchronous operation, the
sampling period T must be in the range
A
T ≤ T ≤ 16 ms. The BTL switches to asynchronous
A,min A
operation outside of this range. If the minimum sampling
time is undercut, the BTL outputs the same position value
several times. The external sampling rate is then greater
than the internal rate. In addition, T
so that the next clock package does not occur in the t
range of the previous package.
t
m
n n+1
LSB
must be long enough
A
m