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INTEGRATED CIRCUITS BLOCK DIAGRAM
SDA55XX
ADC
WDT
Interface
Capture Control
Peripheral
BUS
PWM
Interface
Port Logic
UART
SFRs
71
CI
N
Analog
72
VIN1
Front-end
73
VIN2
74
VIN3
AGC
75
VIN4
2 x ADC
70
VOUT
Analog
1..3
RGB/
Component
YCrCb
79
Front-End
FB
4..6
RGB/
4 x ADC
YCrCb
Memory
RAM
Extension
256x8
STACK
128x8
Memory
Extension / Unit
Counter 0
Counter 1
Interrupt
Contoller
CLOCK &
Sync
System
Adaptive
Color
Comb
Decoder
Filter
NTSC
PAL
NTSC
SECAM
PAL
Saturation
Tint
VPC3230
Y/G
Y
Processing
U/B
Cr
Matrix
Contrast
V/R
Cb
Saturation
Brightness
FB
FB
Tint
AD9883A
54
R
CLAMP
AI
N
48
G
CLAMP
AIN
43
B
CLAMP
AIN
30
HSYNC
SYNC
29
CO AST
PROCESSING
38
AND CLOCK
CLAMP
GENERATIO N
33
FILT
56
SCL
57
SERIAL REGISTER
SD A
AND
55
POWER MANAGEMENT
A
0
Analog / MUX
ADC
PROGRAM ROM
128K x8
CORE
Y
Y
Mixer
2D Scaler
PIP
Panorama
Cr
Cr
Mode
Peacking
Contrast
Cb
Cb
Brightness
2
I
Clock
Gen.
62
63
20.25 MHz
70...77
8
A/D
R
8
2...9
A/D
G
12...19
8
A/D
B
37
MIDSCV
67
DTACK
66
HSOUT
64
VSOUT
65
SOGOU T
58
REF
REF
BYP ASS
AD9883A
64
ADC
Slicer
Acquisition
Acquisition Interface
XRAM
SRAM
BUS
16K x8bit
Arbiter
Caracter
ROM
16K x8bit
RAM / ROM Interface
H
V
Display Logic
DISPLAY GENERATOR
BLANK / COR
CLUT
Display
REGs
FIFO
DAC's
R G
B
31...34
37...40
Output
41...44
Formatter
47...50
ITU-R 656
ITU-R 601
Memory
19...23
Control
27,28
Sync
C Bus
+
Clock
Generation
13,14
2
I
C Bus
OUTA
OUTA
OUTA
First issue 04 / 04
Y OUT
CrCb
OUT
18
YCOE
FIFO
CNTL
LL Clock
56
H Sync
57
V Sync
54
AVO
LCD03B
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