Sony CDX-GT57UPW Manual Del Usuario página 45

CDX-GT57UPW/GT62UMI/GT570UE/GT570UI/GT570UP/GT574UI/GT620UI/GT626UI
Pin No. Pin Name
69 ADVDD3
70 ADIN1 (IN_L-CH)
71 ADVREFL
72 ADVCM
73 ADVREFH
74 ADIN2 (IN_R-CH)
75 ADVSS3
76 MS
CD_BUS0 to
77 to 80
CD_BUS3
81 CD_BUCK
82 CD_XCCE
83 VDD3-2
84 VSS-3
85 /RST
86 VDD1-4
87 DEC_INT
88 BSIF_INT
89 BSIF_GATE
90 BSIF_DATA
91 BSIF_BCK
92 BSIF_LRCK
93 DEC_XMUTE
94 ZDET
95 SP_DATA
96 SP_CLK
97 TEST
98 PDO
99 TMAX
100 LPFN
I/O
- Power supply terminal (+3.3V)
I Audio signal input terminal (L channel)
O Reference voltage output terminal
O Reference voltage output terminal
O Reference voltage output terminal
I Audio signal input terminal (R channel)
- Ground terminal
I I/F mode selection signal input terminal
I Serial data input from the sub system controller
I Serial data transfer clock signal input from the sub system controller
I Chip enable signal input from the sub system controller
- Power supply terminal (+3.3V)
- Ground terminal
I Reset signal input from the main system controller
- Power supply terminal (+1.5V)
O Request signal output to the sub system controller
O Request signal output to the sub system controller
I Gate signal input from the sub system controller
I Audio data input from the sub system controller
I Bit clock signal input from the sub system controller
I L/R sampling clock signal (44.1 kHz) input terminal for audio data input
I Muting on/off control signal input from the sub system controller
O Zero detection signal output terminal
O Spectrum analyzer data output to the sub system controller
I Spectrum analyzer data transfer clock signal input from the sub system controller
I Setting terminal for test mode
O Phase error margin signal between EFM signal and PLCK signal output terminal
O TMAX detection result output terminal
I Inverted signal input from the operation amplifi er for PLL loop fi lter
Description
Fixed at "L" in this unit
Normally fi xed at "L"
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