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ES
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ESPAÑOL, página 75
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DA BLOCK DIAGRAM AND N BLOCK DIAGRAM
DA
(DPU)
CN1101
H.DF
1
REFDC
33
XDC
37
HD OUT
34
HFBP
36
H BLK
15
VS OUT
11
HS OUT
13
PLL LOCK
7
IIC SDA
20
IIC SCL
19
LCC_NS
22
G
HSAW_SW
24
H.LINBAL
16
TO D BOARD
CN502
GYSC
21
GXSC
23
V.DF
2
D.TILT
38
YSC
39
XSC
40
HSHAPE
32
YDC
35
POC
5
DCC2
12
IC1102
VSAWN
10
AMP
3
2
+
4
-
IC1101
DPU
1
HDF1
2
DCC2
3
XDC
21
HDOUT
23
FBP-IN
35
H BLK
36
V-IN
38
H-IN
39
LOCK-DET
40
SDA
41
SCL
43
LCC_NS
44
HSAW_SW
45
PWM2
48
GYSC
49
GXSC
50
VDF
51
VKEY
52
YSC
53
XSC
54
HSHAPE
63
YDC
27
POC-OUT
26
POC-IN
64
DCC
58
ASW1
59
ASW2
5
61
+
VSAWL
7
6
62
-
VSAWH
CN1001
22
LB DET
32
P42/AN10
21
IK SIGMA
34
P41/AN09
51
P86/SDA1
DDC SDA1
7
52
P87/SCL1
DDC SCL1
9
71
P21/A1/A17
DDC GND1
11
49
DDC SDA2
13
P84/SDA2
50
DDC SCL2
15
P85/SCL2
70
DDC GND2
17
P20/A0/A16
80
INPUT SW
29
P27/A7/A23
35
P80/SDA0/SI0
IIC SDA
1
36
P81/SCL0/SO0
IIC SCL
3
37
P82/TXD0
TXD
2
38
RXD
4
P83/RXD0
23
KEY SCAN
35
P42/AN11
79
LED1
33
P26/A6/A22
78
P25/A5/A21
LED2
31
34
P76/SCK0/INT3
PLL LOCK
39
I
31
P73/TB01N0/IN5
POC
40
19
TO D BOARD
HV DET
6
P57/AN07
CN1104
20
ABL DET
8
P40/AN08
28
G2
10
P70/TA1OUT
7
P36/TA7OUT
S6
12
6
P35/TA61N
S5
14
5
P34
S4
16
4
S3
18
P33/MAIT
3
S2
24
P32/HWR
2
S1
26
P31/WR
1
S0
28
P30/RD
58
P04/AD4
PWR SW
23
60
P06/AD6
DGC SW
25
10
V.FBP
30
P61/CTS0
13
WAKE UP
36
P51/AN01
9
ECO SW
5
P60/INT0
INVERTER
Q1001
N
(ı-COM )
— 21 —
IC1001
CPU
CN1003
16
P54/AN04
4
T_AMB
17
P55/AN05
3
VY
18
P56/AN06
2
VX
IC1003
ROM
64
7
WC
P12/A10/AD10
63
6
P11/A9/AD9
SCL
62
5
P10/A8/AD8
SDA
5V
I
46
IC1002
RESET
O
RESET
G
41
X2
X1001
16.9344MHz
43
X1
CPD-E530
E
TO H1 BOARD
CN1400