Interfaces; Ssi Interface (Bml-S1H_-S; Principle; Data Formats - Balluff BML-S1H1-B/S6-C-M3-A-D0-KA S284 Serie Manual De Instrucciones

BML-S1H1/2-B/S6 _ C-M3 _ A-D0-KA _ _ , _ -S284
Absolute Magnetically Coded Position Measuring System
6

Interfaces

6.1 SSI interface
(BML-S1H_-S...)
6.1.1

Principle

SSI stands for Synchronous Serial Interface and describes
a digital synchronous interface with a differential clock line
and a differential data line.
With the first falling clock edge (trigger time), the data
word to be output is buffered in the sensor head. Data
output takes place with the first rising clock edge, i.e. the
sensor head supplies one bit to the data line for each rising
clock edge. In doing so, the line capacities and delays of
drivers t when querying the data bits must be taken into
v
account in the controller.
The max. clock frequency f
length (see Technical data on page 23). The t
called monoflop time, is started with the last falling edge
and is output as the low level with the last rising edge. The
data line remains at low until the t
Afterwards, the sensor head is ready again to receive the
next clock package.
SSI
T
Clk
Clk
1 2 3
Data
MSB
T
Clk
Clk
t
v
Data
T
A
Clk
Data
T = 1/f SSI clock period, SSI clock
Clk Clk
frequency
T = 1/f Sampling period, sampling rate
A A
n Number of bits to be transmitted
(requires n+1 clock impulse)
t = 16 μs Time until the SSI interface is ready
m
again
t = 150 ns Transmission delay times
v
(measured with a 1 m cable)
SSI16
Trigger time
CLK
1 2 3 4
DATA
15 14 13
MSB
Fig. 6-5: Examples of a complete SSI16 data transmission
14 english
is dependent on the cable
clk
time, also
m
time has elapsed.
m
Clock burst
t
m
4 5 n n+1
LSB
t
v
5 6 7 8 9 10
12 11 10 9 8 7
Minimum repeat rate:
T ≥ (n+2) T + t
a clk m
The data output of the BML must be loaded
with 120 Ω, otherwise incorrect measurements
may result.
6.1.2

Data formats

The sensor head has the following factory settings for
position output, which can no longer be changed
retroactively:
– BML-S1H_-S6_C-M3A...: 16 bits,
BML-S1H_-S6_C-M3C...: 18 bits,
BML-S1H_-S6_C-M3F ...: 20 bits
– Binary or gray coded
– Rising or falling
Position values may not be negative. If the value falls below
null, it will jump to the maximum value, i.e.
64/256/1024 mm.
6.1.3

Faulty SSI query

Underclocking
If there are too few clock edges, the current data level will
be maintained for the time t
from Clk. If, however, another positive edge occurs within
the t time, the next bit will then be output. If the t
m
has elapsed, the data output goes to high. The high level is
maintained until the next clock burst.
Overclocking
If there are too many clock edges, the data output will
switch to low after the correct number of cycles has been
completed. The t timer is started again for every
m
additional negative edge from Clk and the T
internally. DATA switches back to high after the time t
elapsed.
11 12 13 14 15 16
6 5 4 3 2 1
LSB
after the last negative edge
m
event is set
m
17
0
time
m
has
m