Biss C Interface (Bml-S1H_-B - Balluff BML-S1H1-B/S6-C-M3-A-D0-KA S284 Serie Manual De Instrucciones

BML-S1H1/2-B/S6 _ C-M3 _ A-D0-KA _ _ , _ -S284
Absolute Magnetically Coded Position Measuring System
6
Interfaces (continued)
6.2 BiSS C interface
(BML-S1H_-B...)
For further information, see
www.biss-interface.com.
The data output of the BML must be loaded
with 120 Ω, otherwise incorrect measurements
may result.
With the BiSS C interface, both position data and register
data can be transmitted bi-directionally. The register data
is transmitted parallel to the position data and has no
effect on the system's measuring behavior. The Balluff
BiSS C sensor heads can be connected to the controller
via a point-to-point connection. The BiSS interface is
compatible to the SSI interface in terms of hardware.
Transmission is CRC-secured, i.e. the controller can check
if the data was received correctly. If the transmission has
failed, the data can be discarded and requested again. The
transmission runs as follows:
– An error and a warning bit are also transmitted.
– Secure bi-directional data transmission is always
available (register communication).
– Runtime compensation of the clock and data line is
possible. This makes it possible to use larger cable
lengths or higher data rates.
Frame
Data
Fig. 6-1: Signal sequence for the BiSS C interface
– With the first rising edge, the controller signals that it is
requesting a value from the sensor head. The position
value valid at this point is included in the data
transmission later on.
– The sensor head confirms the data request with the
second rising edge of the clock by setting low on the
data line.
– The time difference between the second rising edge of
the clock and the first low of the sensor head data line
corresponds to the runtime of both signals. It appears
with all further frame edges and can thus be
compensated for in the controller. This makes it
possible to use much longer cables or higher data
rates than with uni-directional interfaces.
Example: Data with a Clk rate of 1 MHz can be
transmitted by e.g. up to 400 m. Only around 20 m
would be possible without runtime compensation.
www.balluff.com
– All further bits that the sensor transfers are output in
the sensor at the next rising edge.
– The sensor prepares the data during t
completed, the sensor will set the high (start bit) data
signal and then transfer the data. First the CDS bit is
output, the response or echo of the CDM bit that was
sent by the controller in the last frame.
– Afterwards the data is transmitted starting with MSB
and going to LSB.
– One error bit and warning bit each following and the
CRC.
– Register communication:
A bit can be transmitted by the controller to the sensor
head with each frame. To do this, the controller's clock
signal is either set to high or low during t
= 1 µs). The sensor head recognizes it as a high or low
bit (CDM) and mirrors it in the CDS bit in the next
frame. As a result, the controller can detect if the bit
was recognized correctly (secure transmission).
– By transmitting one bit per frame, various addresses in
the sensor head can be read and written over several
frames. Further information on errors or warnings are
also available and it is possible to make a configuration
there.
To ensure the integrity of the data, a cyclic redundancy
check (abbreviated CRC) is used in the controller. Here, a
check value is calculated for the transmitted data in both
the sensor and controller and then compared. If both
values are identical, the data has been transmitted
correctly. If the values are different, the data has been
transmitted incorrectly and the position value must be
requested again.
If the data is backed up, the number of bits of the CRC
value and the CRC polynomial must be set in the controller
in addition to the data length. The length of the CRC value
t
m
can also be calculated from the CRC polynomial and thus
does not need to be indicated in each controller.
t
A
The controller is parameterized as follows:
– Position
BML-S1H_-S6_C-M3A...: 16 bits,
BML-S1H_-S6_C-M3C...: 18 bits,
BML-S1H_-S6_C-M3F...: 20 bits
– 1 error bit
– 1 warning bit
– CRC: 6 bits
The counter polynomial for CRC determination is
0x43 (hex), 67 (dec) or 1000011 (bin).
. Once this is
busy
time (timeout
m
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