Tabla de contenido
Publicidad
Figura 3-11. Funcionamiento del circuito UHS del RFL 9300 durante un fallo interno
Figura 3-12. Funcionamiento del circuito UHS del RFL 9300 durante un fallo externo
RFL 9300
25 de agosto de 2000
B e c a u s e R F L ™ a n d H u b b e l l ® h a v e a p o l i c y o f c o n t i n u o u s p r o d u c t i mp r o v e me n t , we r e s e r v e t h e r i g h t t o c h a n g e d e s i g n s a n d s p e c i fi c a t i o n s wi t h o u t n o t i c e .
2:
2ms dwell time at +12A peak. (Create UHS)
CDT:
Channel Delay Time
CDC:
Channel Delay Compensation
2:
"Reach Forward Time" of 2 ms
6:
Time window of 6 ms that looks for – (11A –
bias setting) peak sample to block UHS.
Correct blocking during this time interval.
(Only 1 sample equal to – (11A – bias
setting) peak, or more negative, is
required to block UHS tripping)
3-10
RFL Electronics Inc.
(973) 334-3100
Publicidad
Tabla de contenido
