Ieee1284 - Brother HL-5130 Manual De Servicios

CAPÍTULO 3 TEORÍA DE OPERACIÓN
1.3.3

IEEE1284

El almacenamiento de datos recibidos desde la PC al DRAM es controlado por el controlador
DMA. Es aplicable a modos de comunicación al recibimiento normal y bidireccional (modo
nibble, modo byte, modo ECP).
74LVX161284, 3.3V
integrado) conecta la resistencia Pull-up a los lados del conector
<HL-5130/5140/5150D>
VDD3
INITN
5C
SEINN
5C
HBUSY
5C
STBN
5C
TP1020
CDCC_D[0]
TP1021
CDCC_D[1]
TP1022
CDCC_D[2]
TP1023
CDCC_D[3]
TP1024
CDCC_D[4]
TP1025
CDCC_D[5]
TP1026
CDCC_D[6]
TP1027
CDCC_D[7]
CDCC_D[7-0]
3A
<HL-5170DN>
230
INITN
5D 229
SEINN
5D
228
HBUSY
5D 227
STBN
5D
CDCC_D[0] 240
239
CDCC_D[1]
CDCC_D[2] 238
235
CDCC_D[3]
234
CDCC_D[4]
CDCC_D[5] 233
232
CDCC_D[6]
CDCC_D[7] 231
CDCC_D[7-0]
3A
5.0V el cambio de nivel de almacenamiento de IC (circuito
L PC Printer
H Printer
CDCC_DIR
3B
CDCC_HD
3B
CDCC_D[7-0]
1C
CDCC_D[0]
CDCC_D[1]
CDCC_D[2]
CDCC_D[3]
CDCC_D[4]
RA7
CDCC_D[5]
10k
CDCC_D[6]
CDCC_D[7]
U5
TP1030
230 245
TP1015
CDCCINITN CDCCACKN
TP1029
229 244
TP1016
CDCCSINN CDCCBUSY
TP1028
228 243
TP1017
CDCCHBUSY CDCCPEN
TP1008
227 242
TP1018
CDCCSTBN CDCCSLCT
241
TP1019
CDCCFLTN
240
CDCC_D0
239 246
CDCC_D1 CDCC_DIR CDCC_DIR INITN_IN
3A 6B
238 250
CDCC_D2 VSCANCLK CDCC_HD SELINN_IN
3A 6B
235
CDCC_D3 HBUSY_IN
6B
234
CDCC_D4 STBN_IN
6B
233
CDCC_D5
232
CDCC_D6
231
CDCC_D7
Aurora
0V
L PC Printer
H Printer PC
48
CDCC_DIR
2B 1
CDCC_HD
2B
34
0V
CDCC_D[7-0]
1C
8
CDCC_D[0]
CDCC_D[1] 9
11
CDCC_D[2]
CDCC_D[3] 12
13
CDCC_D[4]
14
CDCC_D[5]
16
CDCC_D[6]
17
CDCC_D[7]
U7
245 2
CDCCINITN CDCCACKN
244 3
CDCCSINN CDCCBUSY
243 4
CDCCHBUSY CDCCPEN
242 5
CDCCSTBN CDCCSLCT
241 6
CDCCFLTN
CDCC_D0
29
CDCC_D1
INITN_IN
CDC-.cir/2B
28
CDCC_D2 SELINN_IN
CDC-.cir/2B 27
CDCC_D3 HBUSY_IN
CDC-.cir/2B 26
CDCC_D4 STBN_IN
CDC-.cir/2B
CDCC_D5
19
CDCC_D6
24
CDCC_D7
TP999
Aurora
0V
PC
U8
48 18
DIR VCC VDD3
1 7
HD VCC
34 31
0V GND VCC_CABLE VDD5
42
VCC_CABLE
10
GND 0V
15
GND
39
GND
8 41
D[0]
A1 B1
9 40
D[1]
A2 B2
11 38
D[2]
A3 B3
12 37
D[3]
A4 B4
13 36
D[4]
A5 B5
14 35
D[5]
A6 B6
16 33
D[6]
A7 B7
17 32
D[7]
A8 B8
2 47
A9 Y9
3 46
A10 Y10
4 45
A11 Y11
5 44
A12 Y12
6 43
A13 Y13
HBUSY_IN
29 20
C14 A14
SELINN_IN
28 21
C15 A15
INITN_IN
27 22
C16 A16
STBN_IN
26 23
C17 A17
19 30
PLHIN PLH TP998
24 25
HLH HLHIN
TP999
74LVX161284
0V
INITN
2B
SEINN
2B
HBUSY
2B
STBN
2B
Fig. 0-7
U11
18
DIR VCC VDD3
7
HD VCC
31
GND VCC_CABLE VDD5
42
VCC_CABLE
10
GND 0V
15
GND
39
GND
41
D[0]
A1 B1
40
D[1]
A2 B2
38
D[2]
A3 B3
37
D[3]
A4 B4
36
D[4]
A5 B5
35
D[5]
A6 B6
33
D[6]
A7 B7
32
D[7]
A8 B8
47
A9 Y9
46
A10 Y10
45
A11 Y11
44
A12 Y12
43
A13 Y13
20 HBUSY_IN
C14 A14 CDC-.cir/1B
SELINN_IN
21
C15 A15 CDC-.cir/1B
22 INITN_IN
CDC-.cir/1B
C16 A16
23 STBN_IN
C17 A17 CDC-.cir/1B
30
PLHIN PLH TP998
25
HLH HLHIN
74LVX161284
0V D[7-0]
CDC-.cir/3A
INITN
1B
SEINN
1B
HBUSY
1B
STBN
1B
Fig. 0-8
6
0V
D[7-0]
6C
TP118
R78
33
TP119
4B R81
33
TP120
4B
R85
33
TP121
4B
R99 33
4B
DA1 DA2
DF5A6.8FU DF5A6.8FU
0V
D[7-0]
6A
TP122
D[0] RA6
33
1 8
D[1]
2 7
D[2]
3 6
D[3]
4 5
D[4] RA5
33
1 8
D[5]
2 7
D[6]
3 6
TP123
D[7]
4 5
DA3 DA4
DF5A6.8FU DF5A6.8FU
0V
IF_FG
IF_FG2
VDD5
0V
D[7-0]
CDC-.cir/3C
0V
TP118
R113
33
TP119
R115
33
TP120
R119
33
TP121
R131 33
DA2
DA3
ZD1
UDZS6.8B
DF5A6.8FU DF5A6.8FU
0V
TP122
D[0] RA6
33
8
1
D[1]
2 7
D[2]
3 6
D[3]
4 5
D[4] RA5 33
1 8
D[5]
7
2
D[6]
TP123 3 6
D[7]
4 5
DA4 DA5
DF5A6.8FU DF5A6.8FU
0V
IF_FG
IF_FG2
CN6
18
VDD5 +5V
16
0V
17
0V
19
0V
20
0V
21
0V
22
0V
23
0V
24
0V
25
0V
26
0V
27
0V
28
0V
29
0V
30
0V
0V
10
ACK
11
BUSY
12
PE
13
SELECT
32
FLT
14
ATFEED
36
SELIN
31
INPRIM
1
STB
ZD1
UDZS6.8B
2
DI1
3
DI2
4
DI3
5
DI4
6
DI5
7
DI6
8
DI7
9
DI8
15
NC NC
33
NC NC
34
NC NC
35
NC NC
37
FG
38
FG
CN5
18
+5V
16
0V
17
0V
19
0V
20
0V
21
0V
22
0V
23
0V
24
0V
25
0V
26
0V
27
0V
28
0V
29
0V
30
0V
10
ACK
11
BUSY
12
PE
13
SELECT
32
FLT
14
ATFEED
36
SELIN
31
INPRIM
1
STB
2
DI1
3
DI2
4
DI3
5
DI4
6
DI5
7
DI6
8
DI7
9
DI8
15
NC NC
33
NC NC
34
NC
NC
35
NC NC
37
FG
38
FG