Module Control Register (Mcr) - Aventics CANopen Instrucciones De Servicio

156 AVENTICS | CANopen | R412005742–BDL–001–AD
Appendix
13.7.2

Module Control Register (MCR)

The Index 2000 Subindex 0 of the OD contains the 16-bit wide
Module Control Register (MCR). The behavior of the bus coupler
can be changed during operation and in the case of a fault.
Tab. 43 provides an overview of each bit's meaning.
Table 43: Module Control Register
Bit 7 Bit 6 Bit 5
Bit 15 Bit 14 Bit 13
Lowbyte Meaning
Bit 0 Module status in case of error
0 Pre-operational
1 Operational
Bit 2 Bit 1 Outputs in case of error
0 0 CLAB: set outputs to zero (default)
0 1 Last state:
Outputs remain in their last state
1 0 Reserved
1 1 Reserved
Bit 3 EMCY reaction in case of error
0 Emergency telegram is being sent
1 Emergency telegram is not being sent
Bit 4 bis Bit 7 Reserved (fixed at 0)
Bit 8 Input transmission behavior
0 An input change causes: Transmission of all active
PDOs
1 Only the transmission of the PDO, which is assigned
to the input (default)
Bit 9 bis 15 Reserved (fixed at 0)
Low byte
Bit 4 Bit 3 Bit 2
High byte
Bit 12 Bit 11 Bit 10
Bit 1 Bit 0
Bit 9 Bit 8